This application relates to the field of microprocessor architectures, and specifically to cache memory control logic. Processors often use one or more cache memories to reduce memory access time and minimize or eliminate periods when the microprocessor is idle and waiting for data. Cache memories typically store a temporary copies of program instructions and data. Cache memory can be integrated within the same integrated circuit die or same integrated circuit package as the processor, or be an external device interfaced with the processor.
Cache memories are comprised of many cache memory locations, referred to as cache lines. Each cache line typically includes space for storing cached data or instructions (generally referred to as cache data) and a cache tag that uniquely identifies the cache data stored in the cache line. Typically, the cache tag is comprised of all or a portion of the system memory address associated with the original copy of the cache data. Cache lines can also include other data fields to store cache coherency information, which is used to maintain the integrity of the data stored in system memory and any copies stored in the cache memory.
When a processor reads data from memory or writes data to memory, a cache controller identifies one or more cache lines that potentially include a copy of the data. The cache controller compares the tag data of the identified cache lines with all or a portion of the address of the data specified by the processor to determine if one of these identified cache lines actually includes the data specified by the processor. If the cache tag matches the address of the data, a cache hit occurs and the cache controller can retrieve the requested data from the cache memory (if the processor is reading data) or can write the data to cache memory (if the processor is writing data). If the cache tag does not match the address of the data, a cache miss occurs and the processor must read or write the specified data to system memory or a higher level cache memory, if any.
Data stored in cache memories can become corrupted. Data corruption can cause erroneous output data and crash programs and microprocessor systems. To mitigate against data corruption, some cache memories include error detection and/or correction codes. Error detection codes can detect the presence of data errors of one and sometimes more bits in the cache line. Typically, any part of the cache line can become corrupted, including the cache data, the cache tag, and/or cache coherency data. Error correction codes can detect and sometimes correct data errors of one or more bits in the cache lines.
When a processor reads data and the cache memory includes error detection and/or correction codes, the cache controller retrieves the cache tag, the cache data, and the error detection and/or correction code for a cache line. In prior systems, the cache memory controller evaluates the error detection and/or correction code for the cache line to determine if the cache data and cache tag in the cache line is valid or corrupted. If the cache data and cache tag are valid (or if the error correction code can correct any data errors to make the cache data and cache tag valid), then the cache controller compares the cache tag with all or a portion of the address of the specified data to determine if there is a cache hit or a cache miss.
Typically, cache controllers and other part of microprocessors are pipelined to improve performance. Pipelined processors divide data processing into a sequence of pipeline stages connected in series. Each pipeline stage operates independently, allowing different portions of multiple sequential instructions to be processed in parallel, much like an assembly line manufactures multiple items at the same time. Pipelining increases the throughput of data processing operations.
Because evaluating error detection and correction codes and comparing cache tags with addresses requires a substantial amount of time to complete, prior cache controllers implement the error detection and correction evaluation and the cache tag comparison in separate pipeline stages. Because of the need for at least two pipeline stages to implement cache hit/miss evaluation with error detection and correction, performance is degraded as compared with cache controllers that do not include error detection and correction.
It is therefore desirable for a cache controller to provide improved performance with cache memory having error detection and correction. It is also desirable for the cache controller to use error correction codes to minimize the number of cache misses resulting from cache tag data errors. It is further desirable for the cache controller to require minimal additional resources as compared with cache controllers without error detection and/or correction capabilities. It is also desirable for the cache controller to be adaptable to cache memories with error detection only or with error detection and correction.